Constraint-Driven Identification of Application Specific Instructions in the DURASE System

This paper presents a new constraint-driven method for fast identification of computational patterns that is a part of DURASE system (Generic Environment for Design and Utilization of Reconfigurable Application-Specific Processors Extensions). The patterns identified by our system form a base for application specific instruction selection and processor extension generation. Our method identifies all computational patterns directly from an application graph satisfying all architectural and technological constraints imposed by target processors and FPGA devices. The considered constraints include a number of inputs and outputs, a number of operators, and a delay of the pattern critical path. Therefore the identified patterns can be well tailored to target processors. Our approach uses heavily constraint programming methods, which makes it possible to mix graph isomorphism constraints with other constraints in one formal environment. We have extensively evaluated our algorithm on MediaBench and MiBench benchmarks with tough architectural and technological constraints. The obtained patterns have good coverage of application graphs while limiting number of operators and fulfill architectural and technological constraints.